1 Communication processor MPC8272 read and write timing MPC8272 bus read and write access to external devices is realized by the memory control module, the memory control module generates 8 external memory address space chip select signals CSO ~ CS7, each chip select signal corresponding Two main control registers, BR and OR, are used to define the address space defined by the chip select signal and the settings for the number of wait states, the setup time of the read and write strobe signals, the activation time, and the hold time. The MPC8272 reads and writes the timing of external device data as shown in Figure 1 and Figure 2. Where tc is the clock cycle of the external bus operating clock Clock, tRC and tWC are the read and write instruction cycles, respectively, and tW is the clock cycle inserted during the read and write instruction cycle. When the external input signal TA (data transmission acknowledgment signal) is not used, the number of clock cycles inserted is determined by the SCY value of the 0R register, and its value is up to 15 clock cycles; when the external input signal TA is used, the number of clock cycles inserted It is determined by this; when the input signal TA becomes low (that is, when the peripheral data is ready), the processor can complete the reading and writing of the data.
The external bus of the MPC8272 operates at up to 100 MHz. When the read/write instruction cycle is not inserted into the clock cycle, its external bus instruction cycle is 2 clock cycles - 20 ns, and the external bus rate is up to (50 × N) Mbps (where N is the bus data bit width). This rate is very high for general purpose peripherals. The SCY value of the OR register needs to be adjusted to reduce the bus rate and read and write operations of the peripheral. When inserting a maximum of 15 clock cycles, the external bus instruction cycle is up to 17 clock cycles - 170 ns, at which time the external bus rate is at least (5.8 × N) Mbps, which meets the bus read and write requirements of common peripherals. . For some special peripherals of communication, such as switching network circuit MT90826, dual-port RAM IDT71V321, digital signal processor TMS320VC5416 and other interfaces, it is necessary to use the external data transmission confirmation signal TA of the processor MPC8272 and design the corresponding external hardware waiting logic circuit to further reduce The bus rate or dynamically inserts any number of wait clock cycles tW to avoid data read and write collisions, improving processor bus efficiency and data transfer reliability.
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2 Peripheral read and write timing analysis As a voice communication product, the main peripherals of the embedded processor work: the voice switching matrix completes the voice exchange; the DSP completes the DTMF transmission and reception number, the FSK caller number display, and the conference voice integration; the dual port RAM is completed. Data communication between the embedded processor and other processors; the display is used for parameter setting or function display. The bus interface of each peripheral has the characteristics of long read and write cycles and is indeterminate. It cannot be directly connected to the MPC8272 bus. It is necessary to design corresponding external hardware circuits to meet the read and write timing requirements of peripherals. The following describes each peripheral interface separately.
MT90826 is a 4 096 × 4 096 channel non-blocking large voice switching matrix circuit developed by Zarlink, supporting 2.048 Mbps, 4.096 Mbps, 8.192 Mbps and 16.384. ST-BUS format data stream such as Mbps. The circuit uses sequential write control to read the switch, and each output channel corresponds to a connection register. The embedded processor exchanges the input and output channel voice data streams by writing the address of the input channel in the connection register of the output channel. Whether the read/write operation of the MT90826 by the embedded processor is completed can be indicated by the data transmission confirmation signal DTA of the MT90826, and its timing is shown in FIG. When the DTA signal goes from high to low during the chip select cycle, it indicates that the embedded processor can end the read and write operations of the bus. The length of the tAKD is not determined. The maximum value is 240 ns and the minimum value is 0.
In a system, there may be multiple digital signal processors TMS320VC5416, which perform functions such as DTMF transceiving number, FSK caller number display and site voice integration. TMS320VC5416 uses 8-bit HPI interface to exchange data with embedded processor. The communication principle is similar to the dual-port RAM used for data communication between two processors. That is, two processors share a memory space and read and write at different times. operating. When processor 1 is operating (read or write) to a memory address, and processor 2 is also required to operate (write or read), the busy busy signal is output at this time, and processor 2 needs to wait for the busy occupied signal to end. This write or read operation can be completed. The difference between the TMS320VC5416 and the dual-port RAM IDT71V321 is that the embedded processor operates the IDT71V321 as a direct memory operation, while the embedded processor operates the TMS320VC5416 to indirectly manipulate the memory space of the TMS320VC5416 through the HPI interface address and data registers. In addition, the HPI interface busy signal HRDY of the TMS320VC5416 is active high, and the IDT71V321 interface busy signal BUSY is active low. The generation of HRDY and BUSY signals are random, and increase with the increase of bus operating frequency; busy waiting time tRDY and tBUSY also have uncertainty, which is related to the speed of the processor running communication, read and write timing Figure 4 shows.
VGGl2864E is a 128×64 dot matrix OLED display module developed by Beijing Visionox Technology Co., Ltd. The read and write timing is shown in Figure 5. The period tEC of the enable signal E of the OLED module is at least 1 000 ns (equivalent to a fixed 1 Mbps bus rate), and the enable signal pulse width tEH, tEL is at least 450 ns. If the embedded processor MPC8272 directly controls the 0LED module by bus mode, the maximum read and write cycle of the MPC8272 is 170 ns. The read and write timings cannot meet the requirements of the OLED module. It is necessary to design the corresponding external hardware to wait for the logic circuit. Extend the read and write cycle duration of the MPC8272 to meet the requirements of the OLED module.
3 Bus Adaptation Design There are roughly three bus adaptation methods for fast embedded processors and slow peripherals: reducing the external bus frequency, adjusting the chip select control register clock cycles, and using the external input acknowledge signal TA (Intel processor name) The signal RDY is prepared for the data, and the Samsung processor is called the bus cycle extension request signal nwait, which works in the same way).
Reducing the external bus frequency of the embedded processor can lengthen the bus data transfer cycle to match the low-speed peripherals, but greatly reduces the processor utilization and efficiency. This method is not advisable.
Adjusting the number of inserted clock cycles of the embedded processor chip select control register can meet the requirements of peripherals with a fixed bus cycle and no greater than the external bus cycle of the processor, but cannot satisfy the bus cycle uncertainty and greater than the external bus cycle of the processor. Set requirements. For example, the MPC8272 has an external bus operating at 100 MHz and an external bus instruction cycle of up to 170 ns, which satisfies the requirements of peripherals with a bus cycle of less than 170 ns, but cannot be connected to an OLED module (cycle of 1000 ns). Due to the uncertainty of the TMS320VC5416 and IDT71V321 interfaces, the bus cannot be directly connected to the embedded processor bus. It needs to use its external input confirmation signal TA and design external logic circuits for adaptation to meet stable and reliable external bus read and write. Need, its hardware connection is shown in Figure 6. MT90826 data bus interface is 16-bit wide, set MPC8272 chip select CS4 to match 16-bit width; other peripheral data bus is 8-bit wide, share chip select CS5 of MPC8272, and address with high address line A18, A17 Decoding generates a chip select enable signal for other peripherals. The detailed design of CPLDEPM3064 is shown in Figure 7.
In Figure 7, TA_N is the data transmission confirmation signal of MPC8272, active low, and DSP HPI interface data ready signal HRDY is active high, so it must be reversed; dual port RAM busy indication signal (ie data is not ready) BUSY_N is active low and must be inverted; OLED_RDY_N is the data ready signal when the external bus is 100 MHz (SCLK is 100MHz external bus clock input), inserting cnt=100 clock cycles (waiting state is 1μs), low The level is valid. The relevant VHDL of the function module RDY_N is described as follows:
Since the CPLD chip is used here, it is only necessary to modify the value of the parameter cnt in the VHDL program, and the duration of the waiting state can be conveniently adjusted, such as O. 5 μs, 2μs, 3μs, 4μs, etc., is very simple and fast to use. When customizing a fixed 1 Mbps bus rate, you only need to set the cnt value of the chip select to 100, that is, the wait state is 1 μs.
4 Summary <br> The embedded processor MPC8272 memory control module and bus external TA data transmission confirm the input signal, which facilitates the timing matching design of communication with common peripherals and slow peripherals. This paper presents the timing matching method of MPC8272 and various peripherals. The method improves the bus efficiency of the embedded processor and the stability and reliability of the data transmission, and has been used normally in practical engineering applications, and has strong applicability and versatility.
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