This article refers to the address: http://
The use of speech coding technology can effectively reduce the amount of information storage and improve channel utilization. The Hybrid Excitation Linear Prediction (MELP) speech coding algorithm provides high speech quality, naturalness and clarity at lower bit rates and has become the new 2.4 Kb/s speech coding standard of the US Department of Defense. Speech coding technology is playing an increasingly important role in today's digital communications, especially in wireless systems.The Nios II processor is a 32-bit reduced instruction processor soft core from Intel Corporation for Altera Corporation. Load the Nios II soft core and the corresponding peripheral interface and define the corresponding custom instructions in the software SOPC introduced by Altera. Integrate the design and download it into the FPGA to easily implement an embedded processing with high-speed DSP function. [1].
Implementing complex algorithms by hardware is usually more efficient than software implementation. Customized instructions from Altera's Nios II embedded processor allow you to add user-defined functions directly to the arithmetic logic unit (ALU) of the Nios II CPU to speed up the execution of specific tasks. The advantage of custom instructions is that you can change the bottleneck part of the program code to hardware instruction support, and use the custom instructions to speed up the program.
1 Composition of MELP
The sampling rate of the MELP vocoder is 8 kHz, and each sample value is quantized by 16 bits. Each 180 samples is 1 frame, the frame length is 22.5 ms, and the quantization bit number per frame is 54 bit, and the total rate is 2.4 Kb. /s.
The MELP vocoder is based on the traditional binary excitation LPC model, which uses hybrid excitation, aperiodic pulse, adaptive spectral enhancement, pulse shaping filtering and Fourier series amplitude values ​​to make synthesized speech. Can better fit natural speech. Figure 1 shows the block diagram of the MELP codec [2].
2 Nios II can be embedded in the soft core
Nios embedded processor is a user-configurable general-purpose RISC embedded processor. It is a very flexible and powerful processor, so it has become the most popular embedded processor in the world [3]; using the improved Harvard memory structure, The CPU has separate data and program memory bus controls. The SOPC Builder system development tool allows the user to easily specify the connection between the Avalon controller and the slave devices in the system, which can be either memory or peripheral devices.
The Nios instruction bus is 16 bits and is used to read instructions from memory. The Nios data bus is 16-bit or 32-bit wide and is used for 16-bit or 32-bit configurations of the Nios CPU.
2.1 Command System
The Nios instruction system supports C and C++ program compilation, including arithmetic and logic operations, bit operations, byte reads, data transfers, flow control, and conditional transfers. The instruction system includes a rich set of addressing methods to reduce code length and improve processor performance.
2.2 register set
The Nios CPU has a large-capacity windowed general-purpose register set, eight control registers, a program counter, and a K register for the instruction prefix. The general-purpose registers are 16 bits in the 16-bit Nios CPU and 32 bits in the 32-bit Nios CPU. The register bank can be configured to contain 128, 256 or 512 registers. The software can access these registers through a sliding window containing 32 registers. The sliding window is shifted by 16 registers and allows for fast register switching, accelerating the call and return of subroutines.
2.3 Cache
The configurable Nios CPU can optionally contain instruction and data caches. Caches typically improve CPU performance by providing a local storage system that responds quickly to bus events generated by the CPU. The implementation of the Nios cache is a continuous write structure with a simple direct mapping, which is designed to achieve maximum performance with minimal device resources [4].
2.4 Interrupt Processing
The Nios processor allows up to 64 vector interrupts. There are three types of interrupt sources: external hardware interrupts, internal interrupts, and software interrupts. The Nios interrupt processing mode handles all internal interrupts accurately.
The user can selectively disable TRAP instruction software interrupts, hardware interrupts, and internal interrupts. This option can reduce the size of the Nios system, but only for systems where the processor does not run complex software.
2.5 Hardware acceleration
The Nios command system can take advantage of hardware to improve system performance. Special cycle-intensive software operations can significantly improve system performance with hardware, a feature that is provided by modifying the command system [5].
The Nios processor has two instruction system modification methods: custom instructions and standard CPU options [6].
2.5.1 Custom Instructions
Developers can speed time-critical software algorithms by adding custom instructions to the Nios processor instruction system, or they can perform complex processing tasks in single-cycle and multi-cycle operations with custom instructions. In addition, user-added custom instruction logic can access memory and logic outside of the Nios system.
Complex sequences of operations can be simplified in hardware to the execution of a single instruction. This feature allows developers to optimize their software for digital signal processing (DSP), packet header processing, and computationally intensive operations.
Altera's SOPC Builder software provides a graphical user interface (GUI) that developers can use to add up to five custom instructions to the Nios embedded processor.
2.5.2 Standard CPU Options
Altera Corporation provides separate predefined instructions to improve software performance. The MUL and MSTEP instructions are predefined instructions that are implemented with Other hardware. When the user selects these CPU options in SOPC Builder, the associated logic is added to the arithmetic logic unit (ALU). For example, if the user chooses to execute the MUL instruction, the integer multiplier is automatically added to the ALU of the CPU and the 16-bit and 16-bit multiplication operations are completed in 2 clock cycles (the same operation is required if the software program is implemented in a loop) 80 clock cycles).
3 MELP speech coding hardware composition
The hardware circuit board is composed of Altera's FPGA chip EP2C8 as the main control chip. In addition, it also includes: 8 MB SDRAM, 2 MB Flash, WM8731 audio chip, and audio D/A and A/D for debugging. Also comes with a serial port. The MELP speech coding hardware is constructed as shown in Figure 2.
In order to facilitate the debugging of the program, the RS-232 serial port is expanded, which can be directly connected to the serial port of the computer. The 8 MB SDRAM provides the storage space required for the Nios II soft processor to run the embedded operating system. The 2 MB flash also provides storage for MELP software. The WM8731 audio chip provides a fast audio codec data stream and transmits the decoded data stream to the speaker.
WM8731 is a low-power stereo Codec chip with integrated headphone amplification. Therefore, WN8731 can also be applied to MD, DAT and other devices [7]; built-in 24 bit (multi-bit) Σ-Δ triangular modulus Conversion and digital-to-analog conversion, both ADC and DAC use supersampling digital interpolation; digital audio support can be from 16 bit to 32 bit, sample rate from 8 kHz to 96 kHz; stereo audio output with data buffer and digital Volume adjustment, WM8731 is controlled by 2~3 serial interfaces and can work in master-slave mode. The ADC can achieve a signal-to-noise ratio of 90 dB at a 3.3 V signal voltage, and the ADC can achieve a signal-to-noise ratio of 85 dB at a signal voltage of 1.8 V. The DAC signal-to-noise ratio can reach 100 dB at 3.3 V signal voltage, and the DAC signal-to-noise ratio is also 95 dB at 1.8 V signal voltage. Both the ADC and DAC have a frequency response between 8 kHz and 96 kHz, allowing selective use of the high-pass filtering of the ADC. In general, the WM8731 is used in the field of professional sound cards.
The interconnection between the chips is connected to the IO pins of the FPGA through leads. The internal bus of the Nios II processor is connected to the IO via a defined pin, so that the chip that needs to be connected to the Avavon bus can be connected to the bus via the IO pin. Figure 3 shows the connection of the WM8731CODEC chip to the main chip FPGA.
For serial port, SDRAM and Flash use the soft IP based on Avalon bus that comes with Nios II.
This paper discusses the hardware structure of FPGA implementation of MELP hybrid linear code excitation, introduces the main framework of hardware components and MELP codec, and can be used for the preparation of the next software program.
Guangzhou Etmy Technology Co., Ltd. , https://www.digitaltalkie.com