With the development of artificial intelligence technology, robots have begun to take over some of human work, such as express delivery, factory operations, restaurant waiters and even media editors - the New York Times hired a robot to be the editor. In the future, can robots be involved in semiconductor design and development? For example, can a robot perform FPGA development?
Throughout the development of programming languages, from assembly to C to more advanced abstract languages, the threshold for development is lowered, and conventional trivial work is abstracted in high-level languages. For FPGA development, engineers need to master hardware description languages ​​such as VHDL for RTL-level development. Since Xilinx introduced the Vivado design suite three years ago, the FPGA development threshold has been greatly reduced. It is no longer necessary to use the RTL language, using C language. It is possible to complete FPGA development quickly. This is a matter of excitement for software engineers. Previous memory management DMA, interfaces, etc. should be completed by hardware engineers. Now you can write a C language code. Recently, Xilinx released the Vivado Design Suite HLx version of the kit, making FPGA development easier. In the future, it is not a dream to develop FPGAs with robots!
The Vivado HLx release provides design teams with the tools and methods they need to implement C-based design, reuse optimization, IP subsystem duplication, integrated automation, and design convergence acceleration. Combined with the UltraFastTM High-Level Productivity Design Methodology Guide, this special combination is proven to not only help designers work in a high-level abstraction, but also promote reuse, which accelerates productivity.
The new HLx includes the HL system version, the HL design version, and the HL WebPACKTM version. All HLx editions include Vivado High Level Synthesis (HLS) with C/C++ libraries, Vivado IP Integrator (IPI), LogicCORETM IP subsystem, and a complete Vivado implementation tool suite, making it easy for mainstream users to adopt the highest productivity State-of-the-art C language and IP design flow. Combined with the latest UltraFastTM Advanced Productivity Design Methodology Guide, users can increase productivity by 10-15 times compared to traditional methods!
Some people may say that I use RTL to develop and optimize the FPGA. It is not wrong, but it takes more time and manpower. Previously we needed RTL because the logic resources in the FPGA were limited and needed to be better. The trial of optimized logic resources, now, FPGA has a lot of logic resources, and FPGAs are increasingly complex, it is not cost-effective to optimize resources to spend time and manpower. This is the same as software programming. If you use assembly, it will be more efficient, but with C, the development time will be shorter.
Yang Fei, vice president of sales and marketing for Xilinx Asia Pacific, used actual development cases to illustrate the benefits that HLS tools bring to designers. He said that when developing 4G OFDM QAM64 encoding, if designers use traditional methods It takes three months. If you use the Vivado development kit to shorten it to a few days, if you want to develop 4G OFDM QAM256 encoding, the designer is basically impossible to complete with the traditional method, and if you use the Vivado development kit, you can quickly complete the development.
So high-level synthesis tools can free designers from the most cumbersome and basic code development, allowing them to be creative in more advanced work, such as algorithms, modeling, and so on.
In addition, in the era of software-definition, Xilinx has launched a series of SDx development environments (SDSoC, SDAccel and SDNet) to help software engineers in chip design, database development, and next-generation networks easily implement ideas with FPGAs. Expand Xilinx users by 5 times! It is not a dream for software engineers to easily develop innovative applications with FPGAs in the future!
And HLx development tools are not a single tool, Xilinx also considers the construction of the ecosystem, forming an open state, HLx and ecosystem-oriented versions include Vivado HLS, Vivado IPI, LogicCORE IP subsystem and complete Vivado implementation tool suite .
In addition, Xilinx and its Alliance ecosystem continue to expand C libraries for specific markets, such as OpenCV for video and image processing, and machine learning for automotive driver assistance systems (ADAS) and data center applications. Xilinx's new LogiCORE IP subsystem is a highly configurable, market-specific building block that integrates up to 80 different IP cores, software drivers, design paradigms and multiple tests platform. The new IP subsystem is available for Ethernet, PCIe®, video processing, image sensor processing, and OTN development. These IP subsystems use industry standards such as the AMBA® AXI 4 interconnect protocol, IEEE P1735 encryption, and IP-XACT to interoperate with IP from Xilinx and its alliance members and accelerate integration.
Designer-developed C-based IP and pre-packaged IP subsystems can also be combined to automate integration with Vivado IPI. Vivado IPI's integrated automation provides an interactive development environment with device and platform awareness. The environment supports intelligent automatic connectivity of critical IP interfaces, one-click IP subsystem generation, real-time DRC, and interface replacement notifications, as well as powerful debugging capabilities. Platform-aware intelligence provides pre-configured appropriate peripherals, drivers, and memory maps for Zynq® SoC and MPSoC processing systems to support target development boards. Design teams can now quickly identify, reuse, and integrate hardware and software IP cores for ARM® processing systems and high-performance FPGA logic.
So designers can also use their spare time to develop their own IP. These IPs can also become a source of transaction revenue in the future. Similar to Apple's APPstore model, you can develop IOS APP before. Can professional software engineers in the future develop FPGA APP IP?
Back to the topic, software engineers, you can collect FPGA design rules and develop an FPGA robot assistant! I see there is a market!
Circular Emergency Ceiling Light is according to the type can be divided into maintenance or non-maintenance . It is made of solid polycarbonate material , with protection rating of IP65 , suitable for indoor and outdoor use . It comes with a premium rechargeable lithium-ion battery with automatic monthly and annual detection .
Emergency Ceiling Light
Emergency Light Ceiling,Industrial Emergency Light,Led Emergency Ceiling Lights,Ceiling Mounted Emergency Lights
Jiangmen City Pengjiang District Qihui Lighting Electrical Appliances Co., Ltd , https://www.qihuilights.com