The DRV8711 is a stepper motor controller with micro-step function. The micro-step indexer is integrated inside the chip. The configuration can support up to 1/256 microsteps, which greatly reduces the design difficulty of the MCU. In order to reduce the current waveform distortion and obtain smoother motor motion, the chip supports the automatic mixed attenuation mode and the adaptive blanking time function in addition to the fast decay mode and the slow decay mode. At the same time, there are a wealth of protection mechanisms inside the chip, such as overcurrent protection, short circuit protection, undervoltage lockout protection, overtemperature protection and pre-drive error protection, and a FAULTn pin to indicate the fault condition. However, when the bus voltage is high and the layout is not good, it will cause a PDF (pre-driver) error, which makes the chip lock. In this paper, based on the principle of pre-drive error generation, the drive equivalent circuit is analyzed, and the solution of pre-drive error protection false trigger is given.
Figure 1
Figure 1 shows the schematic diagram of the DRV8711 circuit. The pre-driver error is judged inside the chip. That is, during the off period of the lower tube, the chip will perform 2.2us timing. When the timing is over, it will report an error if the voltage of the lower gate source level exceeds 1v.
To analyze the cause of the high Cgs voltage on the chip side, first understand the model of mosfet (as shown in Figure 2). When the upper tube performs the switching action, for example, the upper tube is turned off to on, the drain voltage of the lower tube rises rapidly, and the drain generates a current Ic through the Cgd capacitor to charge Cgs (as shown in FIG. 3). Vgs and Vgd will not change greatly. The injection current Ic can be determined. The injected current will also inject current into the chip through the parasitic inductance. The parasitic inductance and capacitance oscillation cause the pre-drive false trigger on the chip. phenomenon.
Figure 2: Equivalent model of mosfet
(a) Ic generation principle (b) Ic action circuit
Figure 3 Ic action process
Through the above analysis, we can summarize four improvement methods:
Optimize the PCB layout so that the chip drive loop is as short as possible to reduce the size of the parasitic inductance Lleak.
Reduce the value of chip Ic. Because Cgd cannot be changed, Ic can be reduced by changing the source current of the upper tube to reduce dv/dt, specifically by modifying register 0x6h.
The resistor Rdriver is added to suppress the oscillation caused by Lleak, thereby reducing the monitoring voltage at the chip end.
Figure 4 adds the equivalent model of Rdriver
Increasing Cgs to improve, after Cgs becomes larger, the Vgs voltage change caused by the same current Ic becomes smaller.
Four methods are given above, and in general, methods 2 and 3 can solve the problem. Since methods 3 and 4 will reduce the switching speed of the original circuit, resulting in a straight-through phenomenon. Therefore, when using the above method, it is necessary to modify the 0x0h register Dtime to change the dead time to 850 ns.
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